1. Field of the Invention
The present invention relates to a thin film transistor array substrate and fabrication method thereof, and relates to a thin film transistor substrate employed in a liquid crystal display device, for example.
2. Related Background Art
The application of electrical optical elements employing liquid crystals to displays has been the subject of active research. Of these elements, TFT-LCDs which employ thin film transistors (referred to below as TFTs) as switching elements are superior in terms of portability, low electrical power consumption and display quality, and are therefore widely used. In order to attain more widespread usage, further cost reductions are required. As one measure for achieving further cost reductions, the reduction of the number of TFT array fabrication steps for increased productivity has been investigated.
An attempt to eliminate photolithography processes, that is, masks, is illustrated in Japanese Patent Laid-open application No. 2000-111958. A cross-sectional view of a pixel section of a TFT array substrate fabricated by four photolithography processes is shown in FIG. 2A, and the description will be provided using this cross-sectional view.
In this prior art example, after an electrically conductive film with a thickness on the order of 100 nm has been deposited on a transparent substrate, a resist pattern is formed using a first mask in a first photolithography process and gate line 1 is then formed by etching. Next, a gate insulation film 3, a semiconductor layer 4a, and an ohmic layer 4b (described as a xe2x80x98contact layerxe2x80x99 in Japanese Patent Laid-open application No. 2000-111958) are deposited on the transparent substrate on which the gate line 1 is formed so as to have the respective thicknesses 150 to 500 nm, 50 to 150 nm, and 30 to 60 nm. A metal film 16 is then deposited in a thickness of 150 to 300 nm.
In a second photolithography process, a second mask is used to form a resist pattern 17 (described as a xe2x80x98photosensitive filmxe2x80x99 in Japanese Patent Laid-open application No. 2000-111958) thickly on a source electrode 5, source line 6 (described as xe2x80x98data wirexe2x80x99 in Japanese Patent Laid-open application No. 2000-111958), and a drain electrode 7, and thinly in the corresponding section to a semiconductor active layer 8 (described as a xe2x80x98channel sectionxe2x80x99 in Japanese Patent Laid-open application No. 2000-111958). The thick resist pattern on the source electrode 5, source line 6, and drain electrode 7 will be referred to below as the xe2x80x98normal film thickness resist pattern 17a, and the thin resist pattern in the corresponding section to the semiconductor active layer 8 will be referred to below as the thin film resist pattern 17b. The metal film is then removed by wet etching or similar. Thereafter, the thin film resist pattern 17b, the ohmic layer 4b, and the semiconductor layer 4a which lies beneath the ohmic layer 4b are removed at the same time by dry etching. As a result of this processing, the metal film 16 is exposed in the corresponding section to the semiconductor active layer 8. Then, the metal film 16 in the corresponding section to the semiconductor active layer 8 is removed by wet etching to expose the ohmic layer 4b beneath the metal film 16. In addition, part of the semiconductor layer 4a and of the ohmic layer 4b of the corresponding section to the semiconductor active layer 8 are removed by dry etching, whereupon the resist is stripped away. Then SiNx, which constitutes an intermediate insulation film 9, is stacked with a thickness of 300 nm or more. In a third photolithography process, patterning is carried out using a third mask, and the intermediate insulation film 9, and the gate insulation film are then etched. An electrically conductive layer of 40 to 50 nm is also stacked. Ultimately, in a fourth photolithography process, patterning is carried out using a fourth mask and the electrically conductive film is etched, thereby completing the TFT. In the above fabrication method, a reduction of the number of masks is achieved by varying the thickness of the resist of the second mask according to location.
In the fabrication process for a TFT array substrate formed according to the prior art which is shown in FIGS. 16A to 16E, the details of the steps in the second photolithography process are shown. In the prior art illustrated by Japanese Patent Laid-open application No. 2000-111958, the thin film resist pattern 17b, the ohmic layer 4b, and the semiconductor layer 4a which lies beneath the ohmic layer 4b are removed at the same time by dry etching. Further, in the prior art shown in Japanese Patent Laid-open application No. 2001-339072, after the ohmic layer 4b and the semiconductor layer 4a are removed by dry etching, the thin film resist pattern 17b is removed by ashing.
FIG. 16A shows a structure of a TFT array substrate that pertains to a stage in which a resist pattern 17 which comprises the thick normal film thickness resist pattern 17a on the source electrode 5, the source line 6, and the drain electrode 7 and the thin film thickness resist pattern 17b in the corresponding section to the semiconductor active layer 8 is formed, and the metal film 16 is then removed by wet etching or similar. Here, the structure is such that the metal film 16 lies inwards from the ends of the resist pattern 17 as a result of side etching. FIG. 16B shows a structure of the TFT array substrate that pertains to a stage in which the ohmic layer 4b and the semiconductor layer 4a are removed by dry etching, which constitutes the next step. FIG. 16C shows a structure of the TFT array substrate that pertains to a stage in which the thin film resist pattern is removed by ashing, which constitutes the next step. FIG. 16D shows a structure of the TFT array substrate that pertains to a stage in which the metal film 16 in the corresponding section to the semiconductor active layer 8 is removed to expose the ohmic layer 4b beneath the metal film. FIG. 16E shows a structure of the TFT array substrate that pertains to a stage in which part of the semiconductor layer 4a and of the ohmic layer 4b of the corresponding section to the semiconductor active layer 8 is removed by dry etching before the resist is stripped away. At this stage, the source electrode 5, the drain electrode 7, and the semiconductor active layer 8 are exposed.
In the eighth embodiment example of the above-described Japanese Patent application Laid-open No. 2000-111958, following the formation of the resist pattern in the second photolithography process, etching of the metal film is carried out and then the thin resist, the ohmic layer and the semiconductor layer above the channel are removed at the same time. Further, according to Japanese Patent application Laid-open No. 2001-339072, after the ohmic layer and the semiconductor layer are removed by etching, the thin film resist pattern is removed by ashing. The following problems arise with such conventional technology.
Because the photosensitive material of the resist used by the second mask is viscous and fluid, the ends of the resist pattern are shaped with a taper angle. In cases where baking is performed in order to increase the bond strength between the metal film and the resist before the metal film is etched, this inclination becomes prominent. Hence, when the thin resist above the channel is removed, because sections of the thick resist are also tapered in other locations, the ends of the resist pattern are retracted to reduce the surface area of the resist pattern. The smaller the taper angle of the resist pattern, the greater the degree of this retraction.
On the other hand, because the semiconductor layer is removed prior to or at the same time as the removal of the thin film resist pattern, this layer is barely influenced by the area of the resist pattern, that is, by the taper angle of the same. Hence, following the removal of the thin film resist pattern, the pattern ends of the semiconductor layer protrude from the ends of the resist pattern. Even when the semiconductor layer and the thin film resist pattern are removed at the same time, although the ends of the semiconductor layer have a tapered shape, the protrusion from the ends of the resist pattern is similar. The width of this protrusion is determined by the thickness of the resist above the channel which is of reduced thickness and by the taper angle of the pattern ends.
Thereafter, when the metal film in the corresponding section to the semiconductor active layer is removed by etching, the structure is such that the ends of the metal film are contained on the inside of the ends of the resist as a result of side etching. Hence, the structure is such that the semiconductor layer protrudes significantly more than the metal film (the structure in FIG. 16E in which the semiconductor layer protrusion width W is large, for example).
The possibility exists that a TFT transistor array substrate that possesses such a structure will exhibit the characteristic of being extremely sensitive to fluctuations in the luminance due to the effect of the optical conductivity of the protruding semiconductor layer. There is therefore the problem that the TFT characteristics deteriorate due to optical radiation. For example, in cases where this TFT array substrate is used in a liquid crystal display device, when the luminance is made to fluctuate in order to attain an increase in the image quality, the stability of the image quality is severely affected.
It is accordingly an object of the present invention to provide a TFT array substrate and fabrication method thereof, and a liquid crystal display device employing the same which were conceived in order to solve such problems and whereby degradation of the TFT characteristics caused by optical radiation is suppressed.
A fabrication method of a TFT array substrate according to the present invention is a fabrication method of a thin film transistor array substrate having a step of forming a gate line on an insulating substrate; a step of forming a gate insulation film, a semiconductor layer, an ohmic layer, and a metal film on the insulating substrate on which the gate line is formed; a step of forming a pattern of a resist on the metal film by a photolithography process to cover at least a source line, a source electrode, a drain electrode, and a corresponding section to a semiconductor active layer of a thin film transistor which are to be formed on the ohmic layer in following steps, the resist being thinner on the corresponding section to the semiconductor active layer than on other sections; a step of etching the metal film to form the source line, the source electrode and the drain electrode; a step of making the resist thinner to remove the resist on the corresponding section to the semiconductor active layer; a step of removing the ohmic layer and the semiconductor layer of a section excluding the source line, the source electrode, the drain electrode, and the corresponding section to the semiconductor active layer by etching, after removing the resist on the corresponding section to the semiconductor active layer; a step of removing the metal film on the corresponding section to the semiconductor active layer by etching; and a step of removing the ohmic layer on the corresponding section to the semiconductor active layer by etching. This fabrication method makes it possible to fabricate a TFT array substrate whereby degradation of the TFT characteristics which is caused by optical radiation is suppressed.
Another fabrication method of a TFT array substrate according to the present invention is a fabrication method of a thin film transistor array substrate having a step of forming a gate line on an insulating substrate; a step of forming a gate insulation film, a semiconductor layer, an ohmic layer, and a metal film on the insulating substrate on which the gate line is formed; a step of forming a pattern of a resist on the metal film by a photolithography process to cover at least a source line, a source electrode, a drain electrode, and a corresponding section to a semiconductor active layer of a thin film transistor which are to be formed on the ohmic layer in following steps, the resist being thinner on the corresponding section to the semiconductor active layer than on the other sections; a step of etching the metal film to form the source line, the source electrode and the drain electrode; a step of making the resist thinner to remove the resist on the corresponding section to the semiconductor active layer; a step of removing the ohmic layer and the semiconductor layer of a section excluding the source line, the source electrode, the drain electrode, and the corresponding section to the semiconductor active layer by etching, after removing the resist on the corresponding section to the semiconductor active layer; a step of removing the metal film on the corresponding section to the semiconductor active layer by etching; a step of removing the ohmic layer on the corresponding section to the semiconductor active layer by etching; a step of forming an intermediate insulation film; a step of forming a drain electrode contact hole leading to the drain electrode, a source terminal contact hole leading to the source electrode, and a gate terminal contact hole leading to the gate line, in the gate insulation film and the intermediate insulation film by a third photolithography process and etching; a step of forming a conductive film; and a step of forming a pixel electrode covering the drain electrode contact hole, the source terminal contact hole, and the gate terminal contact hole, by a fourth photolithography process and etching. This fabrication method makes it possible to fabricate a TFT array substrate whereby degradation of the TFT characteristics which is caused by optical radiation is suppressed in four photolithography processes.
It is preferable to perform side etching in the step of etching the metal film to form the source line, the source electrode, and the drain electrode. This fabrication method produces a TFT array substrate whereby degradation of the TFT characteristics is suppressed.
It is further preferable that the metal film is removed by 0.5 xcexcm to 1.3 xcexcm by the side etching. This fabrication method produces a TFT array substrate whereby degradation of the TFT characteristics is further suppressed.
Use of a half-tone mask is preferable in photolithography for formation of the resist pattern being thinner on the corresponding section to the semiconductor active layer than on the other sections. It allows to produce a TFT array substrate in four photolithography processes.
Use of a plurality of masks is also preferable in photolithography for the formation of the resist pattern being thinner on the corresponding section to the semiconductor active layer than on the other sections. It allows to produce a TFT array substrate in four photolithography processes.
It is preferable in the formation of the resist pattern being thinner on the corresponding section to the semiconductor active layer than on the other sections that the resist is removed so that ends of the resist pattern are substantially aligned with ends of the metal film.
The source line, the source electrode, and the drain electrode can be made of a metal selected from the group consisting of Cr, Mo, Ti, W, Al and an alloy mainly comprising at least one of the metals.
RIE mode is preferable for ashing to remove the resist on the corresponding section to the semiconductor active layer in order to improve productivity.
It is possible to provide a thin film transistor array substrate whereby degradation of the TFT characteristics is suppressed by the above fabrication method.
The above thin film transistor array substrate is preferably used in a liquid crystal display device. It is thus possible to provide a liquid crystal display device whose image quality is stabile when the luminance is made to fluctuate.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.